第1篇 物理設(shè)計(jì)工程師崗位職責(zé)
芯片物理設(shè)計(jì)工程師 九州華興集成電路設(shè)計(jì)(北京)有限公司 九州華興集成電路設(shè)計(jì)(北京)有限公司,九州華興,九州華興 work with frond-end design team and physical design team for large scale asic chip physical implementation ( hierarchical design ). include top level physical partition , block sizing and shaping , block port assignment, power planning , top/block level p&r implementation .
work for project high quality and on time delivery.
responsibilities :
1. responsible for verilog to gds implementation , power signoff ,area evaluation ,timing closure ,sta,physical verification
2. experienced in eda tools (e.g. synopsys ,candence , mentor etc)
3. critical issue resolve on top congestion or timing issues.
4. better be expert on one or more aspect like : clock tree synthesis /power/physical verification.
skills and knowledge:
1. good knowledge for synthesis , floorplan , place-and-route , timing closure , dfm , dft, power analysis, signal integrity analysis , hierarchical flow
2. good at using script processing.(tcl、perl……)
3. project tapeout experience is needed
4. 28nm and beyond (advanced node) tapeout experience is a good plus.
5. strong verbal communication and interpersonal skills to work closely with a variety of individual
6. team work spirit
qualifications
education and experience
msee with 3+ years or bachelor with 5+ of industrial experience of deep submicron digital asic design.
第2篇 芯片物理設(shè)計(jì)工程師崗位職責(zé)
芯片物理設(shè)計(jì)工程師 九州華興集成電路設(shè)計(jì)(北京)有限公司 九州華興集成電路設(shè)計(jì)(北京)有限公司,九州華興,九州華興 work with frond-end design team and physical design team for large scale asic chip physical implementation ( hierarchical design ). include top level physical partition , block sizing and shaping , block port assignment, power planning , top/block level p&r implementation .
work for project high quality and on time delivery.
responsibilities :
1. responsible for verilog to gds implementation , power signoff ,area evaluation ,timing closure ,sta,physical verification
2. experienced in eda tools (e.g. synopsys ,candence , mentor etc)
3. critical issue resolve on top congestion or timing issues.
4. better be expert on one or more aspect like : clock tree synthesis /power/physical verification.
skills and knowledge:
1. good knowledge for synthesis , floorplan , place-and-route , timing closure , dfm , dft, power analysis, signal integrity analysis , hierarchical flow
2. good at using script processing.(tcl、perl……)
3. project tapeout experience is needed
4. 28nm and beyond (advanced node) tapeout experience is a good plus.
5. strong verbal communication and interpersonal skills to work closely with a variety of individual
6. team work spirit
qualifications
education and experience
msee with 3+ years or bachelor with 5+ of industrial experience of deep submicron digital asic design.
